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1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module)
HYM 361120/40S/GS-60/-70
Advanced Information
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1 048 576 words by 36-bit organization (alternative 2 097 152 words by 18-bit) Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 6820 mW active (-60 version) max. 6160 mW active (-70 version) CMOS - 66 mW standby TTL - 132 mW standby CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh
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12 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible 72 pin Single in-Line Memory Module Utilizes four 1M x 1-DRAMs and eight 1M x 4-DRAMs in 300 mil SOJ packages 1024 refresh cycles/16 ms Tin-Lead contact pads (S - version) Gold contact pads (GS - version) HYM 321140S: single sided module with 31.75 mm (1250 mil) height HYM 321120S: double sided module with 25.40 mm (1000 mil) height
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Ordering Information Type HYM 361140S-60 HYM 361140S-70 HYM 361120S-60 HYM 361120S-70 HYM 361140GS-60 HYM 361140GS-70 HYM 361120GS-60 HYM 361120GS-70 Ordering Code Q67100-Q959 Q67100-Q958 Q67100-Q942 Q67100-Q741 Q67100-Q1019 Q67100-Q651 Q67100-Q961 Q67100-Q960 Package L-SIM-72-8 L-SIM-72-8 L-SIM-72-3 L-SIM-72-3 L-SIM-72-8 L-SIM-72-8 L-SIM-72-3 L-SIM-72-3 Descriptions DRAM module (access time 60 ns) DRAM module (access time 70 ns) DRAM module (access time 60 ns) DRAM module (access time 70 ns) DRAM module (access time 60 ns) DRAM module (access time 70 ns) DRAM module (access time 60 ns) DRAM module (access time 70 ns)
Semiconductor Group
591
06.94
HYM 361120/40S/GS-60/-70 1M x 36-Bit
The HYM 361120/40S/GS-60/-70 is a 4 MByte DRAM module organized as 1 048 576 words by 36-bit in a 72-pin single-in-line package comprising four HYB 511000BJ 1M x 1 DRAMs and eight HYB 514400BJ 1M x 4 DRAMs in 300 mil wide SOJ-packages mounted together with twelve 0.2 F ceramic decoupling capacitors on a PC board. The HYM 361120/40S/GS-60/-70 can also be used as a 2 097 152 words by 18-bits dynamic RAM module by means of connecting DQ0 and DQ18, DQ1 and DQ19, DQ2 and DQ20, ..., DQ17 and DQ35, respectively. Each HYB 511000BJ and HYB 514400BJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 361120/40S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions Pin No. A0-A9 DQ0-DQ35 CAS0 - CAS3 RAS0, RAS2 WE Function Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -60 PD0 PD1 PD2 PD3 -70
VSS VSS
N.C. N.C.
VSS VSS VSS
N.C.
Semiconductor Group
592
HYM 361120/40S/GS-60/-70 1M x 36-Bit
Pin Configuration (top view)
Semiconductor Group
593
HYM 361120/40S/GS-60/-70 1M x 36-Bit
Block Diagram Semiconductor Group 594
HYM 361120/40S/GS-60/-70 1M x 36-Bit
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Soldering temperature ............................................................................................................ 260 C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................... 8.68 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics 1) TA = 0 to 70 C; VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current: -60 version -70 version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) Symbol Limit Values min. max. 5.5 0.8 - 0.4 20 10 V V V V A A 2.4 - 1.0 2.4 - - 20 - 10 Unit Test Condition - - - - - -
VIH VIL VOH VOL II(L) IO(L) ICC1
- -
1240 1120
mA mA
2), 3)
ICC2
-
24
mA
-
Average VCC supply current during RAS ICC3 only refresh cycles: -60 version -70 version (RAS cycling, CAS = VIH , tRC = tRC min.)
2)
- -
1240 1120
mA mA
Semiconductor Group
595
HYM 361120/40S/GS-60/-70 1M x 36-Bit
DC Characteristics (cont'd) 1) Parameter Symbol Limit Values min. Average VCC supply current during fast ICC4 page mode: -60 version -70 version (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) max. Unit Test Condition
2), 3)
- -
840 720
mA mA
ICC5
-
12
mA
-
Average VCC supply current during ICC6 CAS-before-RAS refresh mode: -60 version -70 version (RAS, CAS cycling, tRC = tRC min.)
1)
- -
1240 1120
mA mA
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9) Input capacitance (RAS0, RAS2) Input capacitance (CAS0-CAS3) Input capacitance (WE) I/O capacitance (DQ0-DQ7, DQ9-DQ16, DQ18-DQ25, DQ27-DQ34) I/O capacitance (DQ8, DQ17, DQ26, DQ35) Symbol min. Limit Values max. 80 42 35 80 15 20 pF pF pF pF pF pF - - - - - - Unit
CI1 CI2 CI3 CI4 CIO1 CIO2
Semiconductor Group
596
HYM 361120/40S/GS-60/-70 1M x 36-Bit
AC Characteristics 4) 5) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 361120/40S/GS-60 min. Random read or write cycle time Fast page mode cycle time Access time from RAS Access time from CAS Access time from column address Access time from CAS prech arge CAS to output in low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS pulse width
(fast page mode)
6) 11) 12) 6) 11)
Unit
HYM 361120/40S/GS-70 min. 130 45 - - - - 0 0 3 50 70 70 40 20 70 20 20 15 5 10 0 10 0 15 max. - - 70 20 35 40 - 20 50 - 10000 200000 - - - 10000 50 35 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
max. - - 60 15 30 35 - 20 50 - 10000 200000 - - - 10000 45 30 - - - - - -
tRC tPC tRAC tCAC tAA
110 40 - - - - 0 0 3 40 60 60 35 15 60 15 20 15 5 10 0 10 0 15
6) 12)
tCPA
6) 6) 7) 5)
tCLZ tOFF tT tRP tRAS tRASP tRHCP tRSH tCSH tCAS
CAS precharge to RAS delay RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time CAS precharge time (fast page mode) Row address setup time Row address hold time Column address setup time Column address hold time
.
11)
tRCD tRAD
12)
tCRP tCP tASR tRAH tASC tCAH
Semiconductor Group
597
HYM 361120/40S/GS-60/-70 1M x 36-Bit
AC Characteristics (cont'd) 4) 5) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol Limit Values HYM 361120/40S/GS-60 min. Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time ref. to RAS Write command hold time Write command pulse width
8)
Unit
HYM 361120/40S/GS-70 min. 35 0 0 0 15 15 20 20 0 15 - 0 5 15 0 10 10 10 max. - - - - - - - - - - 16 - - - - - - - ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns
max. - - - - - - - - - - 16 - - - - - - -
30 0 0 0 10 10 15 15 0 15 - 0 5 15 0 10 10 10
tRCS tRCH tRRH
8)
tWCH tWP
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Refresh period Write command setup time CAS setup time CAS hold time RAS to CAS precharge time CAS precharge time Write to RAS precharge time Write to time ref. to RAS
.
13) 13) 13) 10) 13) 13) 9) 9)
tDS tDH tREF tWCS tCSR tCHR tRPC tCP tWRP tWRH
Semiconductor Group
598
HYM 361120/40S/GS-60/-70 1M x 36-Bit
Notes 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 13) For CAS-before-RAS cycles only.
Semiconductor Group
599

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